//`timescale 1ns / 1ps
// You don't need time scale for design files, it is only required in testbench files. 
// The above timescale indicates that simulation unit is 1 ns and the resolution is 1 ns 
////////////////////////////////////////////////////////////////////////////////// 
// Company: Arizona State University 
// Engineer: Brentton Garber
//  
// Create Date:    01:04:04 01/18/2013  
// Design Name:  PED 
// Module Name:    PED  
// Project Name: Lab# 0 
// Target Devices: Xilinx Spartan6 XC6LX16-CS324 
// Tool versions: Xilinx ISE 14.2 
// Description:  
// 
// Dependencies: None 
// 
// Revision:  
// Revision 0.01 - File Created 
// Additional Comments:  
// 
////////////////////////////////////////////////////////////////////////////////// 
module PED(   //Port Declarations
    input i_signal,   // Signal input to be monitored
    input i_clk,      // Synchronous Clock Input
    input i_rst_b,    // An active low input which resets the logic to a default state
    output o_pulse    // A single clock wide pulse to indicate that a Positive edge has
    );           // has been detected
//------------Signal Declarations/Internal Variables-------- 
reg temp_reg_i;       // One clock shifted signal
wire d1_inv_signal_i; // One clock shifted and inverted signal
//-------------Code Starts Here--------- 
always @ (posedge i_clk or negedge i_rst_b) begin
if (i_rst_b == 1'b0) 
  temp_reg_i <= 1'b0;  
else 
  temp_reg_i <= i_signal; 
end 
assign d1_inv_signal_i = !temp_reg_i; 
assign o_pulse = i_signal & d1_inv_signal_i; 
endmodule